Microcontroller User's Manual

4-10 MCF5282 User’s Manual MOTOROLA
Cache Programming Model
Table 4-5 shows the relationship between CACR bits 31, 23, and 22 and the cache
configuration.
Table 4-6 shows the relationship between CACR bits 23, 22, 21 and 20 and setting the
cache invalidate all bit.
3–2 — Reserved, should be cleared.
1–0 CLNF Cache line fill. These bits control the size of the memory request the cache issues to the bus controller
for different initial instruction line access offsets. See Table 4-7 for external fetch size based on miss
address and CLNF.
Table 4-5. Cache Configuration as Defined by CACR[31, 23, 22]
CACR[31] CACR[23] CACR[22] Configuration Description
0 x x N/A Cache is completely disabled
1 0 0 Split Instruction/
Data Cache
1 KByte direct-mapped instruction cache (uses lower half
of tag and storage arrays) and 1 KByte direct-mapped
write-through data cache (uses upper half of tag and storage
arrays)
1 0 1 Instruction Cache 2 KByte direct-mapped instruction cache (uses all of tag
and storage arrays)
1 1 0 Data Cache 2 KByte direct-mapped write-through data cache (uses all
of tag and storage arrays)
Table 4-6. Cache Invalidate All as Defined by CACR[23, 22, 21, 20]
CACR[23] CACR[22] CACR[21] CACR[20] Configuration Operation
0 0 0 0 Split Instruction/
Data Cache
Invalidate all entries in both 1 KByte instruction
cache and 1 KByte data cache
0 0 0 1 Split Instruction/
Data Cache
Invalidate only 1 KByte data cache
0 0 1 0 Split Instruction
Data Cache
Invalidate only 1 KByte instruction cache
0 0 1 1 Split Instruction/
Data Cache
No invalidate
1 0 x x Instruction Cache Invalidate 2 KByte instruction cache
0 1 x x Data Cache Invalidate 2 KByte data cache
Table 4-4. CACR Field Descriptions (continued)
Bits Name Description