Microcontroller User's Manual

3-6 MCF5282 User’s Manual MOTOROLA
Memory Map/Register Set
The additional MAC status register (MACSR) contains a 4-bit operational mode field and
condition flags. Operational mode bits control whether operands are signed or unsigned and
whether they are treated as integers or fractions. These bits also control the
overflow/saturation mode and the way in which rounding is performed. Negative, zero, and
multiple overflow condition flags are also provided.
3.4 Memory Map/Register Set
The EMAC provides the following program-visible registers:
• Four 32-bit accumulators (ACCn = ACC0, ACC1, ACC2, and ACC3)
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit
values for load and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
• One 32-bit MAC status register (MACSR) including four indicator bits signaling
product or accumulation overflow (one for each accumulator: PAV0–PAV3)
These registers are shown in Figure 3-6.
Figure 3-6. EMAC Register Set
3.4.1 MAC Status Register (MACSR)
MACSR functionality is organized as follows:
• MACSR[11–8] contains one product/accumulation overflow flag per accumulator.
• MACSR[7–4] defines the operating configuration of the MAC unit.
• MACSR[3–0] contains indicator flags from the last MAC instruction execution.
Table 3-1 describes MACSR fields.
31 0
MACSR MAC status register
ACC0 MAC accumulator 0
ACC1 MAC accumulator 1
ACC2 MAC accumulator 2
ACC3 MAC accumulator 3
ACCext01 Extensions for ACC0 and ACC1
ACCext23 Extensions for ACC2 and ACC3
MASK MAC mask register
Bit31 12 11–8 76543210
Prod/acc overflow flags Operational Mode Flags
Field — PAVx OMC S/U F/I R/T N Z V EV
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W R/W
Figure 3-7. MAC Status Register (MACSR)