Microcontroller User's Manual

2-32 MCF5282 User’s Manual MOTOROLA
ColdFire Instruction Set Architecture Enhancements
STRLDSR Store/Load Status Register STRLDSR
(Supported Starting with ISA A+)
Operation: If Supervisor State
Then SP - 4 → SP; zero-filled SR → (SP); immediate data → SR
Else TRAP
Assembler Syntax:STRLDSR #<data>
Attributes: Size = word
Description: Pushes the contents of the Status Register onto the stack and then reloads
the Status Register with the immediate data value. This instruction is intended for use as
the first instruction of an interrupt service routine shared across multiple interrupt request
levels. It allows the level of the just-taken interrupt request to be stored in memory (using
the SR[IML] field), and then masks interrupts by loading the SR[IML] field with 0x7 (if
desired). If execution is attempted with bit 13 of the immediate data cleared (attempting
to place the processor in user mode), a privilege violation exception is generated. The
opcode for STRLDSR is 0x40E7 46FC.
Instruction
Format:
1514131211109876543210
0100000011100111
0100011011111100
Immediate Data
Condition
Codes:
X N Z V C X Set to the value of bit 4 of the immediate operand
N Set to the value of bit 3 of the immediate operand
Z Set to the value of bit 2 of the immediate operand
V Set to the value of bit 1 of the immediate operand
C Set to the value of bit 0 of the immediate operand
∗∗∗∗∗
STRLDSR V2, V3 Core (ISA_A) V4 Core (ISA_B) V2 Core (ISA_A+)
Opcode present No No Yes