Microcontroller User's Manual

MOTOROLA Chapter 2. ColdFire Core 2-31
ColdFire Instruction Set Architecture Enhancements
FF1 Find First One in Register FF1
(Supported Starting with ISA A+)
Operation: Bit Offset of the First Logical One in Register → Destination
Assembler Syntax: FF1.L Dx
Attributes: Size = longword
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and
ending with the least-significant bit (Dx[0]), searching for the first set bit. The data register
is then loaded with the offset count from bit 31 where the first set bit appears, as shown
below. If the source data is zero, then an offset of 32 is returned.
Instruction Field:
• Destination Register field—Specifies the destination data register, Dx.
Instruction
Format:
1514131211109876543210
0000010011000 Destination
Register, Dx
Old Dx[31:0] New Dx[31:0]
0b1---- . . . ---- 0x0000 0000
0b01--- . . . ---- 0x0000 0001
0b001-- . . . ---- 0x0000 0002
... ...
0b00000 . . . 0010 0x0000 001E
0b00000 . . . 0001 0x0000 001F
0b00000 . . . 0000 0x0000 0020
Condition
Codes:
X N Z V C X Not affected
N Set if the msb of the source operand is set; cleared
otherwise
Z Set if the source operand is zero; cleared otherwise
V Always cleared
C Always cleared
— ∗∗00
FF1 V2, V3 Core (ISA_A) V4 Core (ISA_B) V2 Core (ISA_A+)
Opcode present No No Yes