user manual

2-10 Computer Group Literature Center Web Site
CPU Modules
2
DRAM Mezzanine Connector (J10)
A 190-pin connector (J10 on the CPX750HA base board) supplies the
interface between the memory bus and the RAM300 DRAM mezzanine.
The pin assignments are listed in the following table.
Table 2-7. DRAM Mezzanine Connector (J10)
1A_RAS∗ A_CAS∗ 2
3B_RAS∗ B_CAS∗ 4
5C_RAS∗ C_CAS∗ 6
7D_RAS∗ D_CAS∗ 8
9OEL∗ OEU∗ 10
11 WEL∗ WEU∗ 12
13 ROMACS∗ ROMBCS∗ 14
15 RAMAEN RAMBEN 16
17 RAMCEN EN5VPWR 18
19 RAL0 GND RAL1 20
21 RAL2 RAL3 22
23 RAL4 RAL5 24
25 RAL6 RAL7 26
27 RAL8 RAL9 28
29 RAL10 RAL11 30
31 RAL12 RAU0 32
33 RAU1 RAU2 34
35 RAU3 RAU4 36
37 RAU5 RAU6 38
39 RAU7 RAU8 40
41 RAU9 RAU10 42
43 RAU11 RAU12 44