user manual

6-42 Computer Group Literature Center Web Site
Subassembly Reference
6
2 GND _GNT# _REQ# _AD31 _AD30 _AD29 GND
1 GND _INTA# _INTB# _INTC# _INTD# _RST# GND
Table 6-34. P4 Connector, HSC Slots 8 and 10
POS
Row
Z Row A Row B Row C Row D Row E
Row
F
25 NP SGA4 SGA3 SGA2 SGA1 SGA0 FG
24 NP GA4 GA3 GA2 GA1 GA0 FG
23 NP +12V CT_RST[n]# CT_EN[n]# -12V CT_MC FG
22 NP PSF0# RSVD RSVD RSVD RSVD FG
21 NP -SELVbat PSF1# RSVD RSVD SELVbat RTN FG
20 NP NP NP NP NP NP NP
19 NP NP NP NP NP NP NP
18 NP VRG NP NP NP VRG RTN NP
NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.
Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued)
POS Row Z Row A Row B Row C Row D Row E Row F
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).