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6-20 Computer Group Literature Center Web Site
Subassembly Reference
6
Table 6-17. P3 Connector, CPU Slots 7 and 9
POS Row Z Row A Row B Row C Row D Row E Row F
19 GND I/O I/O I/O I/O I/O GND
18 GND HS_REQ_ I/O I/O I/O I/O GND
17 GND HS_GNT_ I/O I/O I/O I/O GND
16 GND HS_FLT_ I/O I/O I/O I/O GND
15 GND HS_EJ_ I/O I/O I/O I/O GND
14-1 GND I/O I/O I/O I/O I/O GND
All I/O pins pass through the backplane to the transition module; they do not make any
connection to the backplane.
If the CPU is mounted in slot 7, the HS signals will end with A (for example, HS_REQ_A).
If the CPU is mounted in slot 9, the HS signals will end with B (for example, HS_REQ_B).
Table 6-18. P2 Connector, CPU Slot 7 (Domain A)
POS Row Z Row A Row B Row C Row D Row E Row F
22 GND GA4 GA3 GA2 GA1 GA0 GND
21 GND CLK6 GND RSV RSV RSV GND
20 GND CLK5 GND RSV GND RSV GND
19 GND GND GND RSV RSV RSV GND
18 GND _BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND _BRSVP2
E18
GND
17 GND _BRSVP2
A17
GND _PRST# _REQ6# GNT6# GND
16 GND _BRSVP2
A16
_BRSVP2
B16
_DEG# GND _BRSVP2
E16
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.