user manual

6-18 Computer Group Literature Center Web Site
Subassembly Reference
6
6 GND _IOCS16# I/O _PDIAG# _DA0 _DA2 GND
5GND_DMARQ _IORDY _DIOW# _DMACK# _DIOR# GND
4GND_D14 _D0 I/O _D15 _INTRQ GND
3GND_D3 _D12 _D2 _D13 _D1 GND
2GND_D9 _D5 _D10 _D4 _D11 GND
1GNDI/O _RST# _D7 _D8 _D6 GND
Table 6-16. P4 Connector, CPU Slots 7 and 9
POS Row Z Row A Row B Row C Row D Row E Row F
25 GND _AD36 _AD35 _AD34 _AD33 _AD32 GND
24 GND _AD40 _AD39 _AD38 GND _AD37 GND
23 GND _AD45 _AD44 _AD43 _AD42 _AD41 GND
22 GND _AD49
_+3.3 _AD48 _AD47 _AD46 GND
21 GND _AD53 _AD52 _AD51 GND _AD50 GND
The _+5 and _+3 in the shaded cells are provided by the CPU board; they are not connected to the
system power plane. These signals are prefixed with CPUA if the board resides in slot 7 or CPU
B if the board resides in slot 8 (for example, CPUA_+5).
Signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with L_PCI_A (for example,
L_PCI_A_AD17).
*For boards located in slot 9 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
Table 6-15. P5 Connector, CPU Slots 7 and 9 (continued)
POS
Row
Z Row A Row B Row C Row D Row E
Row
F
Signals in bold text are prefixed with IDE_A if the board resides in slot 7 or IDE_B if the board
resides in slot 9.
Signals in shaded cells are prefixed with F_A if the board resides in slot 7 or F_B if the board
resides in slot 9.
All I/O pins pass through the backplane to the transition module; they do not make any connection
to the backplane.