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Primary (Front) Side CPU Slot Connectors (7 and 9)
http://www.motorola.com/computer/literature 6-17
6
Primary (Front) Side CPU Slot Connectors (7 and 9)
Table 6-15. P5 Connector, CPU Slots 7 and 9
POS
Row
Z Row A Row B Row C Row D Row E
Row
F
22 GND I/O I/O I/O I/O I/O GND
21 GND I/O I/O I/O I/O I/O GND
20 GND I/O I/O I/O I/O I/O GND
19 GND I/O I/O I/O I/O I/O GND
18 GND I/O I/O I/O I/O I/O GND
17 GND I/O I/O I/O I/O I/O GND
16 GND I/O I/O I/O I/O I/O GND
15 GND I/O I/O I/O I/O I/O GND
14 GND I/O I/O I/O I/O I/O GND
13 GND I/O I/O I/O I/O I/O GND
12 GND I/O I/O I/O I/O I/O GND
11 GND I/O I/O I/O I/O I/O GND
10 GND
_TR0# _WPROT# _RDATA# _HDSEL# _DSKCHG
#
GND
9 GND
_MTR1# _DIR# _STEP# _WDATA# _WGATE# GND
8 GND
_RSV1# _INDEX# _MTR0# _DS1# A_DS0# GND
7 GND _CS1FX# _CS3FX# _DA1 _DASP#
_RSV0# GND
Signals in bold text are prefixed with IDE_A if the board resides in slot 7 or IDE_B if the board
resides in slot 9.
Signals in shaded cells are prefixed with F_A if the board resides in slot 7 or F_B if the board
resides in slot 9.
All I/O pins pass through the backplane to the transition module; they do not make any connection
to the backplane.