Technical information

Chapter 2: Hardware Interface Description
December 15, 2009 G30 - Module Hardware Description 45
Reset
To reset the module, RESET_IN must be used (see Table 2-20). This pin performs an external
reset, also called hardware reset. Driving the RESET_IN pin low causes an asynchronous reset of
the entire device except for the Real Time Clock block (RTC). The device then enters its
power-on reset sequence.
Note: As an external reset input, it is recommended that RESET_IN signal will be connected
via a push button, or an open-drain transistor, or an open-collector transistor. In this way,
when RESET_IN signal is not used, It will be at High-Z state. In any case, it is forbidden
to connect this signal directly to any input voltage level.
VREF Reference Regulator
The G30 incorporates a regulated voltage output, VREF. The regulator provides a 2.85V output
for use by the customer application. This regulator can source up to 30 mA of current to power
any external digital circuits.
33 34 GPIO4/SCL O
I
2
C bus clock line (M2M
Zone only)
I
2
C interface
voltage domain.
PU drain.
Value at reset: T/OD.
I/O GPIO
136GPIO5 I/O GPIO Generic digital interfaces
voltage domain.
Output driver class F.
PU/PD class B.
238GPIO6 I/O GPIO Generic digital interfaces
voltage domain.
Output driver class F.
PU/PD class B.
540GPIO7 I/O GPIO Generic digital interfaces
voltage domain.
Output driver class F.
PU/PD class B.
642GPIO8 I/O GPIO Generic digital interfaces
voltage domain.
Output driver class F.
PU/PD class B.
12 GPIO9 I/O GPIO Generic digital interfaces
voltage domain.
Output driver class F.
PU/PD class B.
Table 2-20: Controls and Indicators (Cont.)
Pin #
(81 pin
LGA
interface)
Pin #
(70 pin
connector
interface)
G30
Signal Name
G30
I/O
Function Remarks