Service manual

July 1, 2002 68P81076C25-C
3-28 Theory of Operation: ASTRO Spectra VOCON Board
The DSP program code is stored in the FLASH ROM, U404. During normal modes of operation, the
DSP moves the appropriate program code into the three SRAMs (U401, U402, and U403) and
internal RAM for execution. The DSP never executes program code from the FLASH ROM itself. At
power-up after reset, the DSP downloads 512 words (1536 bytes) from the ROM, starting at $C000,
and puts it into the internal RAM, starting at $0000, where it is executed. This segment of program
code contains the interrupt vectors and the reset vector, and is basically an expanded bootstrap
code. When the MCU messages the DSP that the ADSIC has been configured, the DSP overlays
more code from the ROM into external SRAM and begins to execute it. Overlays occur at different
times when the DSP moves code from the ROM into external SRAM, depending on immediate mode
of operation, such as changing from transmit to receive.
3.3.11 MCU System Clock
The MCU (U701) system clock is provided by circuitry internal to the MCU and is based on the
crystal reference, Y100. The nominal operating frequency is 7.3728 MHz. This signal is available as
a clock at 4XECLK on U701 and is provided to the SLIC (U702) for internal clock timing. The MCU
actually operates at a clock rate of 1/4 the crystal reference frequency or 1.8432 MHz. This clock is
available at ECLK on U701.
The MCU clock contains a crystal warp circuit comprised of L120, Q102, and C162. This circuit is
controlled by an I/O port (PA6) on the MCU. This circuit moves the operating frequency of the
oscillator about 250ppM on certain receive channels to prevent interference from the MCU bus
noise.
3.3.12 DSP System Clock
The DSP (U405) system clock, DCLK, is provided by the ADSIC (U406). It is based off the crystal
reference, Y401, with a nominal operating frequency of 33.0000 MHz. The ADSIC contains an
internal clock-divider circuit that can divide the system clock from 33 MHz to 16.5 MHz or 8.25 MHz
operation. The DSP controls this divider by writing to the ADSIC parallel registers. The frequency is
determined by the processes the DSP is running and, to reduce system power consumption, is
generally configured to the slowest operating speed possible.
The additional circuitry of CR402, L401, C416, C417, C419, and C422 make up a crystal warp
circuit. This circuit is controlled by the OSCw signal from ADSIC, which is configured by the host
through the SPI bus. The crystal warp circuit moves the operating frequency of the oscillator about
400ppM on certain receive channels to prevent interference from the DSP bus noise.
3.3.13 Radio Power-Up/Power-Down Sequence
Radio power-up begins when the user closes the radio on/off switch on the control top, placing 7.5
Vdc on the B+_SENSE line. This signal enables the pass element Q106 through Q105, enabling
SW_B+ to the controller board and the transceiver board. B+_SENSE also enables the +5 Vdc
regulator, U709. When +5 Vdc has been established, it is sensed by the supervisory IC, U726, which
disables the system reset through the delay circuit R208 and C214.
When the MCU comes out of reset, it fetches the reset vector in ROM at $FFFE, $FFFF and begins
to execute the code this vector points to. It configures the SLIC through the parallel bus registers.
Among other things it enables the correct memory map for the MCU. It configures all the transceiver
devices on the SPI bus. The MCU then pulls the ADSIC out of reset and, after a minimal delay, the
DSP also. It then configures the ADSIC via the SPI bus, configuring, among other things, the DSP
memory map. While this is happening, the DSP is fetching code from ROM U404 into internal RAM
and beginning to execute it. It then waits for a message from the MCU that the ADSIC has been
configured, before going on.