Service manual

July 1, 2002 68P81076C25-C
3-26 Theory of Operation: ASTRO Spectra VOCON Board
The MCU executes program code stored in the FLASH ROMs. On a power-up reset, it fetches a
vector from $FFFE, $FFFF in the ROMs and begins to execute code stored at this location. The
external SRAM along with the internal 1Kx8 SRAM is used for temporary variable storage and stack
space. The internal 512 bytes of EEPROM along with the external EEPROM are used for non
volatile storage of customer-specific information. More specifically the internal EEPROM space
contains transceiver board tuning information and on power-down some radio state information is
stored in the external EEPROM.
The SLIC is controlled through sixteen registers mapped into the MCU memory at $1400-$14FF.
This mapping is achieved by the following signals from the MCU: R/W*, CSIO1*, HA0-HA4,HA8,
HA9. Upon power-up, the MCU configures the SLIC including the memory map by writing to these
registers.
The SLIC memory management functions in conjunction with the chip selects provided by the MCU
provide the decoding logic for the memory map which is dependent upon the “map” selected in the
SLIC. The MCU provides a chip select, CSGEN*, which decodes the valid range for the external
SRAM. In addition CSI01* and CSPROG* are provided to the SLIC decoding logic for the external
EEPROM and FLASH ROM respectively. The SLIC provides a chip select and banking scheme for
the EEPROM and FLASH ROM. The FLASH ROM is banked into the map in 16KB blocks with one
32KB common ROM block. The external EEPROM may be swapped into one of the banked ROM
areas. This is all controlled by EE1CS*, ROM1CS*, ROM2CS*, HA14_OUT, HA15_OUT, HA16, and
HA17 from the SLIC (U206) and D0-D8 and A0-16 from the MCU (U204).
The SLIC provides three peripheral chip selects; XTSC1B, XTCS2B, and XTCS3B. These can be
configured to drive an external chip select when its range of memory is addressed. XTSC1B is used
to address the host port interface to the DSP. XTSC2B is used to address a small portion of external
SRAM through the gate U211. XTSCB3 is used as general purpose I/O for interrupting the secure
module.
In bootstrap mode the memory map is slightly different. Internal EEPROM is mapped at $FE00-
$FFFF and F1 internal SRAM starts at $0000-$03FF. In addition, a special bootstrap ROM appears
in the ROM space from $B600-$BFFF. For additional information on bootstrap mode, refer to Section
3.3.6, "Controller Bootstrap and Asynchronous Buses," on page 3-22.
3.3.10 Vocoder Memory Map
The vocoder (DSP) external bus consists of three 32k x 8 SRAMs (U401, U402, and U403), one
256k x 8 FLASH ROM (U404), and ADSIC (U406) configuration registers. Refer to Figure 3-13.
The DSP56001A (U405) has a 24 bit wide data bus (D0-D23) and a 16 bit wide address bus
(A0 - A15). The DSP can address three 64k x 24 memory spaces: P (Program), Dx (Data X), and Dy
(Data Y). These additional RAM spaces are decoded using PS* (Program Strobe), DS* (Data
Strobe), and X/Y*. RD* and WR* are separate read and write strobes.
The ADSIC provides memory decoding for the FLASH ROM (U404). EPS* provides the logic:
and is used as a select for the ROM. The ADSIC provide three bank lines for selecting 16k byte
banks from the ROM. This provides decoding for 128k bytes from the ROM in the P: memory space.
PS* is used to select A17 to provide an additional 128k bytes of space in Dx: memory space for the
ROM.
A15 x (A14
⊕ A13)