Service manual

July 1, 2002 68P81076C25-C
3-24 Theory of Operation: ASTRO Spectra VOCON Board
3.3.7 Vocoder Bootstrap
The DSP has two modes of bootstrap: from program code stored in the FLASH ROM U404, or
retrieving code from the host port.
During normal modes of operation, the DSP executes program code stored in the FLASH ROM,
U404. Unlike the MCU, however, the DSP moves the code from the FLASH ROM into the three
SRAMs, U402, U403, and U414, where it is executed from. Since, at initial start-up, the DSP must
execute this process before it can begin to execute system code, it is considered a bootstrap
process. In this process, the DSP fetches 512 words, 1536 bytes, of code from the FLASH ROM,
starting at physical address $C000, and moves it into internal P memory. This code contains the
system vectors, including the reset vector. It then executes this piece of bootstrap code, which
basically in turn moves additional code into the external SRAMs.
A second mode of bootstrap allows the DSP to load this initial 512 words of data from the host port,
being supplied by the MCU. This mode is used for FLASH programming the DSP ROM when the
ROM may initially be blank. In addition, this mode may be used for downloading some diagnostic
software for evaluating that portion of the board.
The bootstrap mode for the DSP is controlled by three signals; MODA/IRQA*, MODB/IRQB*, and
D23. All three of these signals are on the DSP (U405). MODA and MODB configure the memory
map of the DSP when the DSP reset become active. These two signals are controlled by the ADSIC
(U406) during power-up, which sets MODA low and MODB high for proper configuration. Later these
lines become interrupts for analog signal processing. D23 controls whether the DSP will look for
code from the MCU or will retrieve code from the FLASH ROM. D23 by default is pulled high through
R404 which will cause the DSP to seek code from the FLASH ROM (U404) if this line is read high out
of reset. This line is also connected to an I/O port on the MCU which can configure it for the second,
host port, mode of bootstrap.
3.3.8 Serial Peripheral Interface (SPI) Bus
This bus is a synchronous serial bus made up of a data, a clock, and an individual IC unique select
line. It's primary purpose is to configure the operating state of each IC. ICs programmed by this
include; ADSIC, Synthesizer, Prescaler, DAIC, and, if equipped, the secure module.
The MCU (U204) is configured as the master of the bus. It provides the synchronous clock
(SPI_SCK), a select line, and data (MOSI [Master Out Slave In]). In general the appropriate select
line is pulled low to enable the target IC and the data is clocked in. The SPI bus is a duplex bus with
the return data being clocked in on MISO (Master In Slave Out). The only place this is used is when
communicating with the secure module. In this case, the return data is clocked back to the MCU on
MISO (master in slave out).
3.3.9 Controller Memory Map
Figure 3-12 depicts the controller section memory map for the parallel data bus as used in normal
modes of operation. There are three maps available for normal operation, but map 2 is the only one
used. In bootstrap mode, the mapping is slightly different and will be addressed later.
The external bus for the host controller (U204)) consists of one 32Kx8 SRAM (U202), one 32Kx8
EEPROM (U201), one IMEG FLASH ROM U205, and SLIC (U206) configuration registers. In
addition the DSP host port is mapped into this bus through the SLIC address space. The purpose of
this bus is to interface the MCU (U204) to these devices