Specifications

5 - 2 Symbol SE6700 Integration Guide
Output Data Timing
The sensor’s data output is synchronized with the PCLK output. When LINE_VALID is HIGH, one 8-bit pixel datum
is output every PCLK period.
Figure 5-2 Pixel Data Timing Example
The rising edges of the PCLK signal are nominally timed to occur on the rising PIX_DATA edges. This allows PCLK
to be used as a clock to latch the data. PIX_DATA data is valid on the falling edge of PCLK. The PCLK is HIGH
when the master clock is HIGH, and LOW when the master clock is LOW. It is always enabled, even during the
blanking period.
Figure 5-3 Row Timing and FRAME_VALID/LINE_VALID Signals
LINE_VALID
PCLK
PIX_DATA(7:0)
. . . .
. . . .
. . . .
. . . .
P
0
P
1
PP
3
P
4
P
n-1
P
n
Valid Image Data
Blanking
Blanking
2
. . .
. . .
. . .
FRAME_VALID
LINE_VALID