Digital Photo Keychain User Manual

INSTRUCTION DESCRIPTIONS
A - 48 INSTRUCTION SET DETAILS MOTOROLA
Operation: Assembler Syntax:
D[n] ➞ C; BCLR #n,X:ea
0 ➞ D[n]
D[n] ➞ C; BCLR #n,X:aa
0 ➞ D[n]
D[n] ➞ C; BCLR #n,X:pp
0 ➞ D[n]
D[n] ➞ C; BCLR #n,Y:ea
0 ➞ D[n]
D[n] ➞ C; BCLR #n,Y:aa
0 ➞ D[n]
D[n] ➞ C; BCLR #n,Y:pp
0 ➞ D[n]
D[n] ➞ C; BCLR #n,D
0 ➞ D[n]
Description: Test the n
th
bit of the destination operand D, clear it and store the result in
the destination location. The state of the n
th
bit is stored in the carry bit C of the condition
code register. The bit to be tested is selected by an immediate bit number from 0–23.
This instruction performs a read-modify-write operation on the destination location using
two destination accesses before releasing the bus. This instruction provides a test-and-
clear capability which is useful for synchronizing multiple processors using a shared
memory. This instruction can use all memory alterable addressing modes.
Example:
:
BCLR #$E,X:<<$FFE4 ;test and clear bit 14 in I/O Port B Data Reg.
:
BCLR Bit Test and Clear BCLR
Before Execution After Execution
X:$FFE4
X:$FFE4
$FFFFFF
SR
SR
$0300
$0301
$FFBFFF