User's Manual

68P81093C75-A 11-3
Figure 17. PDR 3500 Functional Block Diagram
SPI Bus
To/From Station
Control Module
SPI Bus
To/From Station
Control Module
Receive
Antenna
RF Input/Output
(Top Panel)
RSS Terminal
(Laptop Typical)
2.1 MHz Ref
2.1 MHz Ref
2.1 MHz Ref
VCO & Ref Mod Audio
AC Input
(Top Panel)
DC Input
(Top Panel)
Switching
Circuitry
+13.8 V
+9.6 V
SW +5 V
LN +5 V
Regulator
Circuitry
RECEIVER MODULE
STATION CONTROL MODULE
POWER SUPPLY MODULE
WIRELINE INTERFACE BOARD
1st
Mixer
21.45 MHz (VHF)
73.35 MHz
(UHF and 800 MHz)
Address
Address
Address
Data
Data
Audio
Interface
Bus
SPI Bus
To/From
Station Modules
TDM Bus
HDLC Bus
VCO & Ref
Mod Audio
HDLC Bus
EXCITER MODULE POWER AMPLIFIER MODULE
2.1 MHz Ref
VCO & Ref
Mod Audio
PA Key
TX Enable
Modulated RF
VHF, UHF
TX Forward Power Detect
+13 DBM
Microprocessor
Power
Control
Circuitry
Synthesizer/
VCO
RF Switch
Circuitry
Differential Data
Data
Data
Data
Address
2.1 MHz Ref
2.1 MHz Ref
External
Speaker
Handset
Transmit
Antenna
Preselector
Filter
3-Pole (UHF)
5-Pole (VHF)
7-Pole (800/900)
Synthesizer/
VCO
Bandpass
Filtering
Custom
Receiver IC
(2nd Injection,
Amplification,
A/D Conversion)
Host
Microprocessor
RSS Host
Interface
Memory
Memory
DSP
ASIC
Digital
Signal
Processor
(DSP)
DSP
ASIC
Interface
Wireline Audio
From Station
To Landline
Wireline Audio
From Landline
To Station
Audio
Interface
Circuitry
2.1 MHz
Reference
Oscillator
Amplifier
Coupler
Peripheral
ASIC
ASTRO
Modem
Microprocessor
Memory
4 - Wire Audio Circuit
Host
ASIC
MAEPF-27042-A
800 MHz
+13
DBM
+21
DBM
IPA
Backplane
Translation
Circuitry
Backplane
Translation
Circuitry