Users Manual Part 1

BR-Arch-2 boot process
U-Boot MTS_BRC_UBOOT-R08.44.03 (Nov 20 2015 - 21:43:13)
CPU0: P1021E, Version: 1.1, (0x80ec0111)
Core: E500, Version: 5.1, (0x80212051)
Clock Configuration:
CPU0:533.333 MHz, CPU1:533.333 MHz,
CCB:266.667 MHz,
DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous),
LBC:66.667 MHz
QE:133.333 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: MTS BR Control
I2C: ready
SPI: ready
DRAM: 1 GB
L2: 256 KB enabled
MMC: FSL_ESDHC: 0
In: serial
Out: serial
Err: serial
Net: eTSEC1, eTSEC2
Hit any key to stop autoboot: 0
CRC32 for 00fff000 ... 00fff003 ==> 2144df1c
CRC32 for 00fff000 ... 00fff003 ==> 5643ef8a
Booting image from bank 1
MMC read: dev # 0, block # 49152, count 1 ... 1 blocks read: OK
MMC read: dev # 0, block # 49152, count 5632 … 5632 blocks read: OK
WARNING: adjusting available memory to 30000000
## Booting kernel from Legacy Image at 01000000 ...
Image Name: MTS_BRC_CORE-R08.44.21
Created: 2016-02-29 10:42:06 UTC
Image Type: PowerPC Enea OSE Kernel Image (gzip compressed)
Data Size: 2675773 Bytes = 2.6 MB
Load Address: 00200000
Entry Point: 00200000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
RTOSE(release). Copyright 2003-2010 Enea Embedded Technology AB. All
rights reserved.
MTS_BRC_CORE-R08.44.21. Copyright 2011-2016 Motorola Solutions Inc.
All rights reserved.
Local Ethernet address: 84:24:8D:0C:1B:55
Local Ethernet address: 84:24:8D:0C:1B:56
Local Ethernet address: 00:14:9F:05:00:12
### Downloading Tetra Application ###
### Press ESC or CTRL-c to interrupt and run Core ###
NOTICE: At this point you can interrupt booting of BR Application and run Core Application. If
you do not interrupt the process, BR continues booting and displays the following output.
### Tetra Application will start automatically within 5 seconds ###
### Press ESC or CTRL-c to run Core or Space to run Tetra Application
instantly ###
6802800U74-AP
Chapter 1: MTS Overview
44