User's Manual

APPLICANT: MOTOROLA EQUIPMENT TYPE: ABZ89FC5812
User / Operational Manual
Functional Description / Operation of Modules and Interconnect (Draft)
EXHIBIT D1-6
Additional Information – Control, Reference, Interconnect
The Host
The host microprocessor is a MPC8250A also known as the Power Quad Integrated Communications Controller II
(PowerQUICC II). The MPC8250 features 64-bit data and 32-bit address busses providing up to 4 GBytes of
address space. The MPC8250 is comprised of a variant of the PowerPC 603e core with Memory Management
Units (MMUs), and a Communication Processor Module (CPM). The MPC8250 is in a 480-pin TBGA package to
allow easier migration to other PowerQUICC processors.
Control and Communications Features
• Microprocessor
— 266 MHz PowerQuicc II Core
— 66 MHz External Bus
— 64-bit (only 32 used) wide 60x Compatible Data Bus, 4 GB Address Space
— 32-bit wide Local Data Bus, 256 KB Address Space
— Separate 16-Kbyte data and instruction caches
— Three User Programmable Machines
— SDRAM Controller
— Virtual DMA for memory to memory and memory to I/O transfers
— 166 MHz Communication Processor Module
— COP/JTAG Test Access Port
— Four General Purpose Timers
— Bus Monitor
— Software Watchdog Timer
— Periodic Interval Timer
— Flexible Interrupt Controller
• Main Memory
— 32 Mbytes of SDRAM, one 32-bits wide bank
— Option to place an additional 96 MB of SDRAM (for a total of 128 MB)
— On board SDRAM components
— 66/133 MHz Device with 9 ns (or faster) Cycle Time
— No Parity Support
• Non-volatile Memory
— 32 MB Compact Flash Memory Card (Application, 16 bit), which can be easily upgraded to larger densities
— One 8/16 MB Flash device (Test app., Boot 0, parameter/data storage, 16 bit)
— On board Flash components
• External Interfaces
— Serial Peripheral Interface (SPI) Bus
— One V.24 / RS-232 Serial Port: Synchronous (Front panel)
— One RS-232 Serial Port, (TXD and RXD only): (Front panel)
— One RS232 / Ethernet CST Port (Front panel)
— Three internal 10/100BaseT Ethernet ports