User's Manual

68P80801H45-1 1/20/2002 23
EBTS System Manual - Vol 2 Base Radio Controllers
900 MHz QUAD Channel Base Radio Controller
parallel-to-serial conversion circuit, connected to the RXDSP data bus. Each
RXDSP communicates to two receive modules through this interface.
Additionally, a serial control path connects the two RXDSPs and the TXDSP. The
Synchronous Communications Interface (SCI) port facilitates this serial control
path.
For initialization and control purposes, one RXDSP connects to the TISIC device.
The TXDSP operates at an external clock speed of 16.8 MHz, provided by the
EXBRC local station reference. The TXDSP internal operating clock is 150MHz,
produced by an internal Phase Lock Loop (PLL).
The TXDSP sends up to four carriers of digitized signal to the EX11 exciter. The
exciter converts the digital signal to analog. Also at the exciter, a highly stable
clock reclocks the digital data. Reclocking enhances transmit signal integrity. Two
framed and synchronized data streams result. One data stream is I-data, and the
other is the Q-data stream.
The TXDSP contains its own, internal address and data memory. The TXDSP can
store 128k words of DSP program and data memory. An eight-bit interface
handles TXDSP-to-host bus communications.
TISIC
The TISIC controls internal DSP operations. This circuit provides the following
functions:
❐ For initialization and control, interfaces with one RXDSP via the DSP
address and data buses.
❐ Accepts a 16.8 MHz signal from Station Reference Circuitry.
❐ Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from
the site reference.
❐ Demodulates the 1 PPS
❐ Outputs a 1 PPS signal and a windowed version of this signal for network
timing alignment.
❐ Outputs a 2.4 MHz reference signal used by the Exciter.
❐ Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS time
mark. The system decodes the time mark from the site reference. Then the
system routes the reference to the TXDSP and RXDSPs.)
Station Reference Circuitry
The Station Reference Circuitry is a phase-locked loop (PLL). This PLL consists of
a high-stability, Voltage-Controlled, Crystal Oscillator (VCXO) and a PLL IC. GPS
output from the iSC connects to the 5 MHz/1 PPS BNC connector on the BR
backplane. Wiring at this connector routes signals to EXBRC station reference
circuitry.
The PLL compares the 5 MHz reference frequency to the 16.8 MHz VCXO output.
Then the PLL generates a DC correction voltage. The PLL applies this correction
voltage to the VCO through an analog gate. The analog gate closes when three