User's Manual

20 68P80801H45-1 1/20/2002
Base Radio Controllers EBTS System Manual - Vol 2
900 MHz QUAD Channel Base Radio Controller
Serial Communication Buses
The microprocessor provides a general-purpose SMC serial management
controller bus.
The SMC serial communications bus is an asynchronous RS-232 interface with no
hardware handshake capability. The BRC front panel includes a nine-pin, D-type
connector. This connector provides a port where service personnel may connect a
service computer. Service personnel can perform programming and maintenance
tasks via Man-Machine Interface (MMI) commands. The interface between the
SMC port and the front- panel STATUS connector is via EIA-232 Bus Receivers
and Drivers.
Host Processor
The microprocessor incorporates 4k bytes of instruction cache and 4k bytes of
data cache that significantly enhance processor performance.
The microprocessor has a 32-line address bus. The processor uses this bus to
access non-volatile memory and SDRAM memory. Via memory mapping, the
processor also uses this bus to control other BRC circuitry.
The microprocessor uses its Chip Select capability to decode addresses and assert
an output signal. The eight chip-select signals select non-volatile memory,
SDRAM memory, input ports, output ports, and DSPs.
The Host processor...
❐ Provides serial communications between the Host Microprocessor and other
Base Radio modules.
❐ Provides condition signals necessary to access SDRAM.
❐ Accepts interrupt signals from BRC circuits (such as DSPs).
❐ Organizes the interrupts, based on hardware-defined priority ranking.
❐ The Host supports several internal interrupts from its Communications
Processor Module. These interrupts allow efficient use of peripheral
interfaces.
❐ The Host supports 10 Mbps Ethernet/IEEE 802.3.
❐ Provides a 32-line data bus transfers data to and from BRC SDRAM and
other BRC circuitry. Buffers on this data bus allow transfers to and from
non-volatile memory, general input and output ports and DSPs.
Non-Volatile Memory
Base Radio software resides in 2M x 32 bits of FLASH memory. The Host
Microprocessor addresses the FLASH memory with 20 of the host address bus’ 32
lines. The host accesses FLASH data over the 32-line host data bus. A
host-operated chip-select line provides control signals for these transactions.
The FLASH contains the operating system and application code. The system
stores application code in FLASH for fast recovery from reset conditions.
Application code transfers from network or site controllers may occur in a