User's Manual

18 68P80801H45-1 1/20/2002
Base Radio Controllers EBTS System Manual - Vol 2
900 MHz QUAD Channel Base Radio Controller
900 MHz QUAD Channel Base Radio Controller Theory of Operation
Table 10 briefly describes the BRC circuitry. Figure 13 is a functional block
diagram of the BRC.
Host Microprocessor
The host microprocessor is the main controller for the BR. The processor operates
at a 50-MHz clock speed. The processor controls Base Radio operation according
to station software in memory. Station software resides in FLASH memory. For
normal operation, the system transfers this software to non-volatile memory. An
EEPROM contains the station codeplug.
NOTE
At BR power-up, the EXBRC LED indicates a major
alarm. This indication continues until BR software
achieves a predetermined state of operation.
Afterward, the software turns off the EXBRC LED.
Table 8 900 MHz QUAD Channel BR Controller Controls
Control Description
RESET Switch A push-button switch used to manually reset the BR.
STATUS
connector
A 9-pin connector used for connection of a service computer, providing a
convenient means for testing and configuring.
Table 9
Pin-outs for the STATUS Connector
Pin-out Signal
1 not used
2 TXD
3 RXD
4 not used
5 GND
6 not used
7 not used
8 not used
9 not used