User's Manual

68P80801E35-B 5/1/2002 13
EBTS System Manual - Vol 2 Base Radio Controllers
Enhanced Base Radio Controller
For initialization and control purposes, the RXDSP connects to the TISIC device.
The TXDSP operates at an external clock speed of 16.8 MHz, provided by the
EBRC local station reference. The TXDSP internal operating clock is 150MHz,
produced by an internal Phase Lock Loop (PLL).
The TXDSP sends one carrier of digitized signal to the TISIC to reformat the date
before sending it to the exciter. The exciter converts the digital signal to analog.
The TXDSP contains its own, internal address and data memory. The TXDSP can
store 128k words of DSP program and data memory. An eight-bit interface
handles TXDSP-to-host bus communications.
TISIC
The TISIC controls internal DSP operations. This circuit provides the following
functions:
❐ For initialization and control, interfaces with the RXDSP via the DSP
address and data buses.
❐ Accepts a 16.8 MHz signal from Station Reference Circuitry.
❐ Accepts a 5 MHz signal, modulated with one pulse per second (1 PPS) from
the site reference.
❐ Demodulates the 1 PPS from the modulated 5 MHz signal
❐ Outputs a 1 PPS signal and a windowed version of this signal for network
timing alignment.
❐ Outputs a 2.1 MHz reference signal used by the Exciter and Receiver(s).
❐ Generates 15 ms and 7.5 ms ticks. (These ticks synchronize to the 1 PPS time
mark. The system decodes the time mark from the site reference. Then the
system routes the reference to the TXDSP and RXDSP.)
❐ Provides a 4.8 MHz reference signal. This signal is used by the Exciter to
clock data into the TRANLIN
❐ Accepts differential data from the Receiver(s) (Rx through Rx3) via the
interface circuitry.
❐ Transmits serial control data to the Receiver(s) (Rx through Rx3) via the
serial data bus.
❐ Accepts and formats differential data from the TXDSP for transmission to
the Exciter via interface circuitry.
❐ Generates the Receiver SSI (RxSSI) frame sync interrupt for the RxDSP.
Station Reference Circuitry
The Station Reference Circuitry is a phase-locked loop (PLL). This PLL consists of
a high-stability, Voltage-Controlled, Crystal Oscillator (VCXO) and a PLL IC. GPS
output from the iSC connects to the 5 MHz/1 PPS BNC connector on the BR
backplane. Wiring at this connector routes signals to EXBRC station reference
circuitry.
The PLL compares the 5 MHz reference frequency to the 16.8 MHz VCXO output.
Then the PLL generates a DC correction voltage. The PLL applies this correction