Service manual
GCAP_INT
TSTATE2
MCLK
INT_CS
Europe Middle East & Africa Customer Services 26.07.99
LEVEL 3 AL SCHEMATICS Rev. 1.0
Tai Chi P5 Version P5
Michael Hansen, Ray Collins, Ralf Lorenzen Page 2 of 3
REVISIONS
TAI CHI - Organiser V.P5
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
13 MHz REFERENCE CLOCK
TEXT REFERENCE SIGNALS
DATA BUS
ADDRESS BUS
V2
TDO
TRST*
TCK
V2
TMS
EMU1
TDI
EMU0
EMU1
UTXD
URXD
CTS
URTS_PA5
BATT_SER_DATA
V2
Q803
URTS_PA5
DCS_TXD
DCS_RXD
SIMPD0
SVENO
TIMING7
TIMING8
CLK_SELECT
SIM_RX
SIM_TX
EMU0
TCK
TMS
TRST*
TDO
TDI
RESET
CE1
CEO
R_W
CE3
CE2
CE4
CE5
DBGACK
IRQ
FIQ
TSIZE
TSTROBE*
TSTATE0
TSTATE1
BCLKX
BDX
BCLKR
BDR
OWDAT
U703
TX_EN
DM_CS
TX_KEY
DP_EN
ADDRESS (21:0)
SR_VCC
V2
U702
U701
VRVA_INT
CE8
RX_ACQ
RFI
RCLOCK
RX_EN
PC_TXD
PC_RXD
J600
MQSPI_CS2
DSP_CLK_OUT
SW_RF
V2
BATT_FDBK
DR2
DX2
MQSPI_CLK2
MQSPI_CS0
KBC4
KBC3
KBC2
KBC1
KBC0
KBR4
KBR3
KBR2
SR_CS
V2
V2
V2
KBR1
KBR0
BOOM_EN
-5V_EN
EXT_CHG
PB12
PB11
PB10
INTR_OUT2
VIB_EN
BKLT_EN
V1 V1
DOWNLINK_GCAP
UPLINK_GCAP
MAN_TEST_AD
UPLINK
Q912
Q911
DOWNLINK
EXT B+
DSC_EN
BATT+
DOWNLINK AD
DSC_EN_AD
J611
Q710
V2 DCABLE_INT
LS_V1
INTR_OUT1
CHRG_EN
PB5
PB4
PB3
PB2
LED_RED
LED_GRN
V3
HS_INT
TEST_ENH
GCLK
VRVA_INT
DCABLE_INT
HEAD_INT
V2
STDBY
Q628
THERM
J612
J614
J613
J610
BATT_SER_DATA
BATT_THERM
STDBY
V2
V1
V2
RESET
V2
BATT+
B+
B+
RTC_BATT
DR1
DX1
MQSPI_CLK1
MQSPI_CS1
MAGIC 13MHz
WDOG
Y900
LS_V1
VSIM_1
V3
B+
Q920
Q921
VREF
Q960
UPLINK
Ext B+
VS944
AUX_BATT_THERM
BATT_THERM
DSC_EN_AD
DOWNLINK_AD
MANTEST_AD
V_BOOST1
PWR_SW
CLKIN
Q901
Q902
VIB_EN
B+
U801
J810
BATT+
B+
Q972
Ext B+
Q932
V2
V_BOOST1LS_V1
DOWNLINK
V2
SPI_CLK
SPI_DR
V2
SR_CS
SR_VCC
J910
V2
GCAP_CLK
VCLK
VDR
VDX
VFSRX
SPI_DW
SPI_CE
PAGE UP
PAGE DOWN
HOME
POWER
KBRO
KBR1
KBR2
KBC0
KBC1
KBC2
KBC3
BATT+
BATT FDBK
Q635
CHRG_EN
Q634
Ext B+
VREF
BATT+
B+
BOOM_EN
SPK-
Q981
BOOM_PWR
U980
VAG
ALRT_VCC
B+
Q938
-5V
LS_V1
-5V_EN
HS_INT
PWR_SW
V2
HS_INT
SPK+
SPK-
RTC_BATT
V2 V2
V2
V2
THERM
U950
BATT+
Q805
Q805
LED_RED
LED_GRN
KBR2
U901
V2KBC1
SPEAK_TP915
V2
B+
VAG
U980
HS_MIC
J504
V2
HEAD_INT
SIM_TX
SIM_TX
SIM_RX
HEAD_INT
V2 VSIM1
VSIM1
PD
RST
KBC1
KBR3
KBR0
RTC Batt
KBC2
KBC0
I/O
CLK
SPK+
SPK-
U940
DATA (15:0)
WHITECAP
U700
U701
EPROM
U702
SRAM
BFSR
U900
GCAP 4.0