Service manual

at the same time as the Audio CODEC interrupt. An ARM interrupt is
generated to synchronize the ARM megamodule to the DSC interrupt. The
DSC time slots are the basic data structures in the DSC module. The function
of the DSC is to transmit and receive DSC frames on the DSC bus. These
frames may come from or be sent to the Lead DSP Audio Coder XIO port, the
ARM Call Processor PIF port, or the Manchester coded DSC bus.
The DSC module in Whitecap operates only in the Master mode at a
controllable bit rate of 128kHz or 512kHz. The audio CODEC clock always
operates at 512Khz. Switching the DSC from 128kHz to 512kHz is held off
until DSC time slot boundaries. This functionality is changed from BIC 4.X for
the Whitecap DSC module to accommodate the CODEC interface and
synchronization for the Lead DSP.
2. UART-RS232
The UART is based upon a TL16C550 compatible UART. It is used to
communicate serially over an RS232 interface. The module sends and
receives characters of 8 bits. The number of stop bits can be programmed to
1 or 2. Parity can be programmed to even, odd, or disabled completely. The
module contains a 32 deep FIFO for the received characters and a 16 deep
FIFO for transmit. It generates its own baud rate based upon a programmable
divisor and its input clock.
3.SIM INTERFACE
The SIM Interface is a peripheral in the Whitecap Chip that allows the ARM
Core to communicate with pre-paid cards or SIM cards. It communicates with
the ARM via the 16-bit internal Peripheral Bus. The SIM interface contains 2
ports, one allowing synchronous or asynchronous ( pre-paid cards ) serial
transmission and the other allowing only asynchronous serial transmission.