Service manual

microphone inputs can be selected. These inputs are EXT_MIC, the output of the
differential input microphone amplifier, A3 or , the output of the differential
auxiliarymicorphone amplifier, A5.
These three inputs are single ended with respect to VAG.
Note that MIC IN+ should be DC connected to VAG to avoid an offset relative to the
A/D input. MIC_BIAS is derived from VAG for best noise performance. MB_CAP
bypasses the gain from VAG to MIC_BIAS to keep the noise balanced.
Following the input stage and multiplexer is a selectable gain stage and
30kHz low-pass antialiasing filter. This lowpass filter may be designed to
whatever order is needed to insure that aliased components are not present in
the output. The gain of the selectable gain stage can be selected in 1dB steps
from -7dB to +8dB. Depending on the design of the A/D converter the output
of the antialiasing filter may be clamped to keep from overdriving the A/D
converter.
The audio input A/D converter converts the incoming signal to 13-bit 2's
compliment linear PCM words at an 8 or 8.1 kHz rate. Following the A/D
converter, the signal is digitally filtered, low-pass and selectable high-pass.
The audio input bits control the configuration of the input section. These bits
select the gain, enable or disable the input, select between the EXT_MIC, A5
amplifier output, or A3 amplifier output, and select or deselect the high pass
input filter. Also, these bits can select a loopback mode that takes the digital
output of the input A/D converter, and loops it directly back to the D/A output
section for testing.
WhiteCap Logic Interfaces
1.DSC Module
The DSC module implements the GSM Data Speech Control interface in the
Whitecap IC. It accepts manchester encoded data input on the DSC bus and
generated manchester coded data onto the DSC bus. DSC data may be
transmitted to or received from the TI LEAD megamodule or TI ARM
megamodule via the XIO interface and PIF interface, respectively. The PIF
interface also provides control of the DSC module.
The DSC module generates a clock and frame sync to the audio codec
interface. The frame sync is synchronized so the DSC LEAD interrupt occurs