Service manual

input CLK4 output
MQSPI CS1
Ball G5,
input
CE
Ball L8,
output
MQSPI CS1
DR1
Ball P5,
output
DR1
DX1 (SPI_DATA): Serial Peripheral Interface Data, Data will be transmitted
from WhiteCap to the
MAGIC IC. Data will be latched into MAGIC either on rising edge or falling
edge of clock depending on the control bit settings.
MQSPI_CLK : Clock used to shift data out serially.
MQSPI_CSI : Chip select signal used to latch data into MAGIC.
DR1 : Not connected to MAGIC .
MAGIC will interface with the Serial Peripheral Interace 1 (SPI1) of the WHITECAP
IC. Data on the bus will be changed on the fallling edge of the clock and sampled on
the rising edge. The IC will only accept data if a valid chip select is given (active
high) and data is latched in on the falling edge of MQSPI_CS1. There are 4
groups of SPI bits. Data is written most significant bit first. Each SPI transfer
must consist of the full 64 bit field. Thus, additional dummy bits must be
padded to those sequences which are not full length. The two most significant
bits are used to select which SPI group is addressed.
7.2 Logic circuitry
7.2.1 GSM Logic
We call the GSM signal processing control circuit as GSM logic. GSM logic
employed two main chip for its operations – WhiteCap and GCAP-II.
There are two function parts in WhiteCap which provides digital signal processing
and general control.
The WhiteCap IC is a digital processing IC for GSM radiotelephones. It
contains a TI cLEAD DSP core, a TI ARM/Thumb microcontroller core and
custom peripherials implemented in TI’s TSC5000 ASIC standard cell
technology. This part will be used for s/w and radio development.
The DSP core contains 80K words of DSP RAM for software development.
The production version of this part will store DSP and ARM boot-code in on-
chip ROM.
Whitecap contains the following:
• ARM7TDMIE core (Thumb 32/16 bit micro controller core)
• cLEAD Mega Module (DSP w/ 80K words RAM + ARM-API + BBIF-API
+ SP + DPLL)