User manual

3.3 Address Decoding and Lockout Circuitry
Since some addresses below 2000 (hex) are located on the KIM-1 board, the
data bus buffers are used to isolate KIM-1 from the motherboard whenever these
addresses below 2000 are issued. This function is provided by U5, which is
connected to the three high-order address lines (AB13, 14, 15). If any of
those address lines go high (indicating an address above 2000), then the data
bus buffers will be enabled in the appropriate direction. The data buffers will
also be enabled if an address between 0400 and 13FF (indicated by the Kl, K2,
K3, and K4 lines) is present.
There are six locations in the memory space which have special
significance in any 6502-based system. These are locations FFFA through FFFF.
These locations contain the values for the interrupt vectors for the NMI, RST,
and IRQ control lines. In the KIM-1 system, these interrupt vectors are stored
in locations 17FA - 17FF, the six highest memory locations in KIM-1 since the
three highest address lines are not decoded on KIM-1. Since the full KIM system,
including the motherboard, does use all sixteen address lines, it is necessary
to detect when one of these six highest addresses is issued by the processor
and force the data to be read from KIM-1 rather than any memory on the motherboard.
This function is provided by U7. Whenever the thirteen high-order address lines
are all at logic 1, this condition is detected by U7 and the signal generated is
used to disable U5. When U5 is disabled, the decode line generated as the output
of U5 goes to a logic 1. This is inverted in U3 and becomes the decode enable
line which is fed back to the KIM-1. The motherboard addressing is turned off
and the addressing on KIM-1 is turned on, allowing the reset, NMI, and IRQ
vectors to be fetched from the high six memory locations in KIM-1. Thus, even
with a fully expanded KIM system, these three control vectors will still be under
the control of the KIM monitor.