Technical information

Micro-KIM Users Manual
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Looking at figure 14, there are 40 pins. Pin 1 is labeled on the board and is near the edge at the upper-left corner
of the connector. Here is a description of the 40 pins
1 and 40 there are two pins for ground to give proper grounding to optional expansion boards.
2 VCC, this is a 5V signal which powers the circuit
3-14, 31-38 These are the CPU address lines A0-A15 used to address memory or devices
11 R/W this is the read/write signal. Low when writing, high when reading memory
12-15, 26-29 These are the CPU data bus. Used to transfer data to/from RAM/EPROM or devices
16 Sync. This signal goes high during when an instruction is being fetched for the CPU
17 NMI. Non-Maskable Interrupt signal to the CPU. Active low to generate
18 DEN, Onboard memory decode Enable line. Control the enabling of the onboard memory
19 IO3 is the pre-decoded signal for the 2
nd
optional 6532. Attach to CS1 pin 38 on 6532
20 PHI1 Phase 1 clock signal. 180 degrees from phase 2
21 IRQ Interrupt request signal. Active low generates an IRQ.
22 PB7 is I/O port pin PB7 from 6532 required to complete cassette interface
23 SST Single step signal used to control CPU with single step
24 TAPE this signal is used to complete the cassette interface. See figure 15 for future information
25 RDY used to stop the CPU in single step circuit
30 PHI2 phase 2 main clock signal to the 6502
39 RESET 6502 RESET line, when pulled low will reset the 6502
Figure 15: KIM-1 cassette circuit showing removed section and TAPE signal location