Specifications

Intel

810E2 Chipset Platform

Design Guide 99

3.22. LPC/FWH

The following provides general guidelines for compatibility and design recommendations for supporting

the FWH flash BIOS device. The majority of the changes will be incorporated in the BIOS.

3.22.1. In-Circuit FWH Programming

All cycles destined for the FWH will appear on the PCI. The ICH2 hub interface-to-PCI Bridge puts all

processor boot cycles out on the PCI (before sending them out on the FWH interface). If the ICH2 is set

for subtractive decode, these boot cycles can be accepted by a positive decode agent on PCI. This

enables booting from a PCI card that positively decodes these memory cycles. To boot from a PCI card,

it is necessary to keep the ICH2 in the subtractive decode mode. If a PCI boot card is inserted and the

ICH2 is programmed for positive decode, two devices will positively decode the same cycle. In systems

with the 82380AB (ISA bridge), it is also necessary to keep the NOGO signal asserted when booting

from a PCI ROM. Note that it is not possible to boot from a ROM behind the 82380AB. Once you have

booted from the PCI card, you potentially could program the FWH in circuit and program the ICH2

CMOS.

3.22.2. FWH Vpp Design Guidelines

The Vpp pin on the FWH is used for programming the flash cells. The FWH supports a Vpp of 3.3 V or

12 V. If Vpp is 12 V, the flash cells will program about 50% faster than at 3.3 V. However, the FWH

only supports 12 Vpp for 80 hours. The 12 Vpp would be useful in a programmer environment that is

typically an event that occurs very infrequently (much less than 80 hours). The VPP pin MUST be tied to

3.3 V on the motherboard.

In some instances, it is desirable to program the FWH during assembly with the device soldered down on

the board. In order to decrease programming time it becomes necessary to apply 12 V to the V

pin.

The following circuit will allow testers to put 12 V on the V

pin while keeping this voltage separated

from the 3.3 V plane to which the rest of the power pins are connected. This circuit also allows the

board to operate with 3.3 V on this pin during normal operation.

Figure 59. FWH VPP Isolation Circuitry

FET

12V 3.3V

VPP