Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 97
There are four pins which are used to put the 82562ET/EM controller in different operating states:
Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for
this design.
Test_En Isol_Tck Isol_Ti Isol_Tex State
0 0 0 0 Enabled
0 1 1 1 Disabled w/ Clock (low power)
1 1 1 1 Disabled w/out Clock (lowest power)
The four control signals shown in the above table should be configured as follows: Test_En should be
pulled-down through a 100 Ω resistor. The remaining 3 control signals should each be connected through
100 Ω series resistors to the common node “82562ET/EM_Disable” of the disable circuit.
3.21.5. Intel
®
82562ET / 82562EH Dual Footprint Guidelines
These guidelines characterize the proper layout for a dual-footprint solution. This configuration enables
the developer to install either the 82562EH or the 82562ET/82562EM components, while using only one
motherboard design. The following guidelines are for the 82562ET/82562EH dual-footprint option. The
guidelines called out in Sections 3.21.1 through 3.21.4 apply to this configuration. The dual footprint for
this particular solution uses a SSOP footprint for 82562ET and a TQFP footprint for 82562EH. The
combined footprint for this configuration is shown in the following two figures.
Figure 57. Dual-Footprint LAN Connect Interface
dual_ft_lan_conn
ICH2
LAN_TXD[2:0]
LAN_RXD[2:0]
LAN_RSTSYNC
LAN_CLK
L
8
2
5
6
2
E
T
S
S
O
P
Stub
82562EH
TQFP