Specifications

Intel

810E2 Chipset Platform

92 Design Guide

Distance from Intel

82562EH to Magnetics Module

Due to the high speed of signals present, distance ‘A’ between the 82562EH and the magnetic should

also be less than 1”, but should be second priority relative to distance from connects to the magnetic

module.

Generally speaking, any section of trace intended for use with high-speed signals should be subject to

proper termination practices. Proper signal termination can reduce reflections caused by impedance

mismatches between the device and trace route. The reflections of a signal may have a high-frequency

component that may contribute more EMI than the original signal itself.

Distance from LPF to Phone RJ11

This distance ‘C’ should be less then 1”. Regarding trace symmetry, route differential pairs with

consistent separation and with exactly the same lengths and physical dimensions.

Asymmetrical and unequally long differential pairs contribute to common-mode noise. This can degrade

the receive circuit performance and contribute to emissions radiated from the transmit side

3.21.4. Intel

82562ET / 82562EM Guidelines

Related Documents

• 82562ET Platform LAN Connect (PLC) Datasheet

• PCB Design for the 82562 ET/EM Platform LAN Connect

For correct LAN performance, designers must follow the general guidelines outlined in Section 3.21.2.

Additional guidelines for implementing a 82562ET or 82562EM LAN connect component are as

follows.

3.21.4.1. Guidelines for Intel

82562ET / 82562EM Component Placement

Component placement can affect the signal quality, emissions, and temperature of a board design. This

section provides guidelines for component placement.

Careful component placement can:

• Decrease potential problems directly related to electromagnetic interference (EMI), which could

result in failure to meet FCC and IEEE test specifications.

• Simplify the task of routing traces. To some extent, component orientation will affect the

complexity of trace routing. The overall objective is to minimize turns and crossovers between

traces.

It is important to minimize the space needed for the Ethernet LAN interface, because all other interfaces

will compete for physical space on a motherboard near the connector edge. As with most subsystems, the

Ethernet LAN circuits must be as close as possible to the connector. Thus, it is imperative that all designs

be optimized to fit in a very small space.