Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 9
Figure 51. Intel
®
82562EH Termination ................................................................................... 90
Figure 52. Critical Dimensions for Component Placement ...................................................... 91
Figure 53. Intel
®
82562ET/82562EM Termination ................................................................... 93
Figure 54. Critical Dimensions for Component Placement ...................................................... 94
Figure 55. Termination Plane................................................................................................... 96
Figure 56. Intel
®
82562ET/EM Disable Circuit ......................................................................... 96
Figure 57. Dual-Footprint LAN Connect Interface.................................................................... 97
Figure 58. Dual-Footprint Analog Interface .............................................................................. 98
Figure 59. FWH VPP Isolation Circuitry................................................................................... 99
Figure 60. Filter Topology ...................................................................................................... 100
Figure 61. Filter Specification................................................................................................. 101
Figure 62. Using Discrete R................................................................................................... 103
Figure 63. No Discrete R........................................................................................................ 103
Figure 64. Core Reference Model.......................................................................................... 104
Figure 65. Schematic of RAMDAC Video Interface ............................................................... 105
Figure 66. RAMDAC Component and Routing Guidelines .................................................... 107
Figure 67. Recommended RAMDAC Reference Resistor Placement and Connections....... 108
Figure 68. Recommended LC Filter Connection.................................................................... 109
Figure 69. Frequency Response (see Table 30) ................................................................... 111
Figure 70. Test Load vs. Actual System Load ....................................................................... 122
Figure 71. Aggressor and Victim Networks............................................................................ 124
Figure 72. Transmission Line Geometry: (A) Microstrip (B) Stripline..................................... 124
Figure 73. One Signal Layer and One Reference Plane........................................................ 127
Figure 74. Layer Switch with One Reference Plane .............................................................. 128
Figure 75. Layer Switch with Multiple Reference Planes (same type) ................................... 128
Figure 76. Layer Switch with Multiple Reference Planes ....................................................... 128
Figure 77. One Layer with Multiple Reference Planes........................................................... 129
Figure 78. Overdrive Region and V
REF
Guardband................................................................ 131
Figure 79. Rising Edge Flight Time Measurement................................................................. 132
Figure 80. Intel
®
810E2 Chipset Clock Architecture............................................................... 135
Figure 81. Different Topologies for the Clock Routing Guidelines ......................................... 138
Figure 82. Example of Capacitor Placement Near Clock Input Receiver .............................. 139
Figure 83. Example of Clock Power Plane Splits and Decoupling......................................... 141
Figure 84. Power Delivery Map.............................................................................................. 144
Figure 85. G3-S0 Transistion................................................................................................. 145
Figure 86. S0-S3-S0 Transition.............................................................................................. 146
Figure 87. S0-S5-S0 Transition.............................................................................................. 147
Figure 88. Pull-up Resistor Example ..................................................................................... 149
Figure 89. Example 1.8V/3.3V Power Sequencing Circuit..................................................... 152
Figure 90. Example 3.3V/V5REF Sequencing Circuitry......................................................... 153
Figure 91. GMCH Power Plane Decoupling........................................................................... 155
Figure 92. USB Data Line Schematic .................................................................................... 167
Figure 93. SPKR Circuitry ...................................................................................................... 171
Figure 94. V5REF Circuitry .................................................................................................... 172
Figure 95. Host/Device Side Detection Circuitry .................................................................... 174
Figure 96. Device Side Only Cable Detection........................................................................ 174
Figure 97. BCLK Waveform ................................................................................................... 182
Figure 98. Processor System Bus Valid Delay Timings......................................................... 183
Figure 99. Processor System Bus Setup and Hold Timings .................................................. 183
Figure 100. Power-On Reset and Configuration Timings ...................................................... 183