Specifications
Intel
®
810E2 Chipset Platform
R
Design Guide 89
3.21.3.2. Guidelines for Intel
®
82562EH Component Placement
Component placement can affect the signal quality, emissions, and temperature of a board design. This
section discusses guidelines for component placement.
Careful component placement can:
• Decrease potential problems directly related to electromagnetic interference (EMI), which could
result in failure to meet FCC specifications.
• Simplify the task of routing traces. To some extent, component orientation will affect the
complexity of trace routing. The overall objective is to minimize turns and crossovers between
traces.
It is important to minimize the space needed for the HomePNA LAN interface, because all other
interfaces will compete for physical space on a motherboard near the connector edge. As with most
subsystems, the HomePNA LAN circuits must be as close as possible to the connector. Thus, it is
imperative that all designs be optimized to fit in a very small space.
3.21.3.3. Crystals and Oscillators
To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges.
Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals
should also be kept away from the HomePNA magnetics module to prevent communication interference.
If they exist, the crystal’s retaining straps should be grounded to prevent the possibility of radiation from
the crystal case, and the crystal should lie flat against the PC board to provide better coupling of the
electromagnetic fields to the board.
For noise-free and stable operation, place the crystal and associated discrete components as close as
possible to the 82562EH. Minimize the length and do not route any noisy signals in this area.
3.21.3.4. Phoneline HPNA Termination
The transmit/receive differential signal pair is terminated with a pair of 51.1-Ω (1%) resistors. This
parallel termination should be placed close to the 82562EH. The center, common point between the
51.1-Ω resistors is connected to a voltage-divider network. The termination is shown in the following
figure.










