Specifications

Intel
®
810E2 Chipset Platform
R
88 Design Guide
to ground. Using capacitors with capacitances exceeding a few pF in either of these locations can
slow the 100-Mbps rise and fall times so much that they fail the IEEE rise time and fall time
specifications. This will cause the return loss to fail at higher frequencies and will degrade the
transmit BER performance. Caution should be exercised if a cap is put in either of these locations.
If a cap is used, it should almost certainly be less than 22 pF. (Reasonably good success has been
achieved by using 6-pF to 12-pF values in past designs.) Unless there is some overshoot in the
100-Mbps mode, these caps are not necessary.
Note: It is important to keep the two traces within a differential pair close to each other. Keeping them close
helps to make them more immune to crosstalk and other sources of common-mode noise. This also
means lower emissions (i.e., FCC compliance) from the transmit traces and better receive BER for the
receive traces. Close should be considered to be less than 0.030 inches between the two traces within a
differential pair (0.007 inch trace-to-trace spacing is recommended).
3.21.3. Intel
®
82562EH Home/PNA* Guidelines
Related Documents
Title Location
Intel
®
82562EH HomePNA 1-Mb/s Physical Layer
Interface Datasheet (Order number: 278313)
Intel’s website for developers is at:
http://developer.intel.com
Intel
®
82562EH HomePNA 1-Mb/s Physical Layer
Interface Brief Datasheet (Order number: 278314)
Intel’s website for developers is at:
http://developer.intel.com
For correct LAN performance, designers must follow the general guidelines outlined in Section 3.21.2.
Additional guidelines for implementing a 82562EH Home/PNA* LAN connect component are listed in
the following sections.
3.21.3.1. Power and Ground Connections
Obey the following rule for power and ground connections:
• For best performance, place decoupling capacitors on the back side of the PCB, directly under the
82562EH, with equal distance from both pins of the capacitor to power/ground.
The analog power supply pins for 82562EH (VCCA, VSSA) should be isolated from the digital VCC
and VSS through the use of ferrite beads. In addition, adequate filtering and decoupling capacitors
should be provided between VCC and VSS as well as the VCCA and VSSA power supplies.