Specifications

Intel
®
810E2 Chipset Platform
R
86 Design Guide
Comply with the following rules to help reduce circuit inductance in both backplanes and motherboards:
• Route traces over a continuous plane with no interruptions (i.e., do not route over a split plane). If
there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This
will increase inductance and EMI radiation levels.
• To reduce coupling, separate noisy digital grounds from analog grounds.
• Noisy digital grounds may affect sensitive DC subsystems.
• All ground vias should be connected to every ground plane, and every power via should be
connected to all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This minimizes the loop area.
• Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain many
high-frequency harmonics that can radiate EMI.
• The ground plane beneath the filter/transformer module should be split. The RJ45 and/or RJ11
connector side of the transformer module should have chassis ground beneath it. Splitting the
ground planes beneath the transformer minimizes noise coupling between the primary and
secondary sides of the transformer and between adjacent coils in the transformer. There should not
be a power plane under the magnetics module.
• Create a spark gap between pins 2 through 5 of the Phoneline connector(s) and shield ground of
1.6mm (59.0 mil). This is a critical requirement needed to past FCC part 68 testing for Phoneline
connection.
Note: For worldwide certification a trench of 2.5 mm is required. In North America, the spacing
requirement is 1.6 mm. However, home networking can be used in other parts of the world,
including Europe, where some Nordic countries require the 2.5 mm spacing.
3.21.2.3. A 4-Layer Board Design
Top-Layer Routing
Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight
control of signal integrity and removes any impedance inconsistencies due to layer changes.
Ground Plane
A layout split (100 mils) of the ground plane under the magnetics module between the primary and
secondary side of the module is recommended. It is also recommended to minimize the digital noise
injected into the 82562 common ground plane. Suggestions include optimizing decoupling on
neighboring noisy digital components, isolating the 82562 digital ground using a ground cutout, etc.
Power Plane
Physically separate digital and analog power planes must be provided to prevent digital switching noise
from being coupled into the analog power supply planes VDD_A. Analog power may be a metal fill
“island,” separated from digital power, and better filtered than digital power.
Bottom-Layer Routing
Digital high-speed signals, which include all LAN interconnect interface signals, are routed on the
bottom layer.