Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 83
3.21.1.5. Crosstalk Consideration
Noise due to crosstalk must be carefully minimized. Crosstalk is the main cause of timing skews and is
the largest part of the t
RMATCH skew parameter.
3.21.1.6. Impedances
Motherboard impedances should be controlled to minimize the impact of any mismatch between the
motherboard and the add-in card. An impedance of 60 Ω ± 15% is strongly recommended. Otherwise,
signal integrity requirements may be violated.
3.21.1.7. Line Termination
Line termination mechanisms are not specified for the LAN connect interface. Slew-rate-controlled
output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and
ringback. A 33-Ω series resistor can be installed at the driver side of the interface, if the developer has
concerns about over/undershoot. Note that the receiver must allow for any drive strength and board
impedance characteristic within the specified ranges.
3.21.2. General LAN Routing Guidelines and Considerations
3.21.2.1. General Trace Routing Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on
sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to
decrease interference from other signals, including those propagated through power and ground planes.
Observe the following suggestions to help optimize board performance:
• The maximum mismatch between the clock trace length and the length of any data trace is 0.5”.
• Maintain constant symmetry and spacing between the traces within a differential pair.
• Keep the signal trace lengths of a differential pair equal to each other.
• Keep the total length of each differential pair under 4”. (Many customer designs with differential
traces longer than 5” have had one or more of the following issues: IEEE phy conformance failures,
excessive EMI, and/or degraded receive BER.)
• Do not route the transmit differential traces closer than 100 mils to the receive differential traces.
• Do not route any other signal traces both parallel to the differential traces and closer than 100 mils
to the differential traces (300 mils is recommended).
• Keep to 7 mils the maximum separation between differential pairs.
• For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90° bend
is required, it is recommended to use two 45° bends instead. Refer to the following figure.
• Traces should be routed away from board edges by a distance greater than the trace height above the
ground plane. This allows the field around the trace to couple more easily to the ground plane rather
than to adjacent wires or boards.
• Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the
clock. And as a general rule, place traces from clocks and drives at a minimum distance from
apertures, by a distance exceeding the largest aperture dimension.