Specifications

Intel
®
810E2 Chipset Platform
R
82 Design Guide
Table 24. LOM/CNR Length Requirements
Configuration A B C D
Intel
®
82562EH 0.5” to 6.0” 4.0” to (10.0” – A)
Intel
®
82562ET 0.5” to 7.0” 3.0” to (10.0” – A)
Dual footprint 0.5” to 6.5” 3.5” to (10.0” – A)
Intel
®
82562ET/EH card* 0.5” to 6.5” 2.5” to (9” – A) 0.5” to 3.0”
NOTES:
1. The total trace length should not exceed 13”.
Additional guidelines for this configuration are as follows:
• Stubs due to the resistor pack should not be present on the interface.
• The resistor pack value can be 0 Ω or 22 Ω.
• LAN on Motherboard PLC can be a dual-footprint configuration.
3.21.1.4. Signal Routing and Layout
LAN connect signals must be carefully routed on the motherboard to meet the timing and signal quality
requirements of this interface specification. The following are some of the general guidelines that should
be followed. It is recommended that the board designer simulate the board routing, to verify that the
specifications are met for flight times and skews due to trace mismatch and crosstalk. On the
motherboard, the length of each data trace is either equal in length to the LAN_CLK trace or up to 0.5”
shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard trace in each
group.)
Figure 48. LAN_CLK Routing Example
LAN_CLK
LAN_RXD0