Specifications

Intel
®
810E2 Chipset Platform
R
80 Design Guide
Table 22. LAN Design Guide Section Reference
Layout Section Figure Ref. Design Guide Section
Intel
®
ICH2 – LAN interconnect A Section 3.21.1 Intel® ICH2 – LAN Interconnect Guidelines
General routing guidelines B,C,D Section 3.21.2 General LAN Routing Guidelines and
Considerations
Intel
®
82562EH B Section 3.21.3 Intel® 82562EH Home/PNA* Guidelines
Intel
®
82562ET /82562EM C Section 3.21.4 Intel® 82562ET / 82562EM Guidelines
Dual layout footprint D Section Intel
®
82562ET/EM Disable Guidelines 82562ET/EM
Disable Guidelines
3.21.1. Intel
®
ICH2 – LAN Interconnect Guidelines
This section contains the guidelines for the design of motherboards and riser cards that comply with LAN
connect. It should not be considered a specification, and the system designer must ensure through
simulations or other techniques that the system meets the specified timings. Special care must be taken to
match the LAN_CLK traces with those of the other signals, as follows. The following guidelines are for
the ICH2-to-LAN component interface. The following signal lines are used on this interface:
• LAN_CLK
• LAN_RSTSYNC
• LAN_RXD[2:0]
• LAN_TXD[2:0]
This interface supports both 82562EH and 82562ET/82562EM components. Both components share
signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0]. Signal lines
LAN_RXD[2:1] and LAN_TXD[2:1] are not connected when 82562EH is installed.
3.21.1.1. Bus Topologies
The LAN connect interface can be configured in several topologies:
• Direct point-to-point connection between the ICH2 and the LAN component
• Dual footprint
• LOM/CNR implementation