Specifications

Intel
®
810E2 Chipset Platform
R
8 Design Guide
Figures
Figure 1. Intel
®
810E2 Chipset System ....................................................................................20
Figure 2. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET) ..........29
Figure 3. Routing for THRMDP and THRMDN.........................................................................31
Figure 4. BSEL[1:0] Circuit Implementation for PGA370 Designs ...........................................33
Figure 5. Examples for CLKREF Divider Circuit.......................................................................34
Figure 6. RESET# Schematic for PGA370 Designs.................................................................35
Figure 7. Capacitor Placement on the Motherboard.................................................................37
Figure 8. TAP Connector Comparison .....................................................................................38
Figure 9. Component Keep-Out Zones ....................................................................................39
Figure 10. Nominal Board Stackup...........................................................................................42
Figure 11. GMCH Quadrant Layout (top View).........................................................................42
Figure 12. Intel
®
ICH2 Quadrant Layout (Top View).................................................................43
Figure 13. Firmware Hub (FWH) Packages .............................................................................44
Figure 14. uATX Placement Example for PGA370 Processors ...............................................45
Figure 15. System Memory Topologies....................................................................................46
Figure 16. System Memory Routing Example ..........................................................................47
Figure 17. System Memory Connectivity..................................................................................48
Figure 18. Display Cache (Topology 1) ....................................................................................49
Figure 19. Display Cache (Topology 2) ....................................................................................49
Figure 20. Display Cache (Topology 3) ....................................................................................50
Figure 21. Display Cache (Topology 4) ....................................................................................50
Figure 22. Hub Interface Signal Routing Example ...................................................................51
Figure 23. Single Hub Interface Reference Divider Circuit.......................................................53
Figure 24. Locally Generated Hub Interface Reference Dividers .............................................53
Figure 25. Intel
®
ICH2 Decoupling Capacitor Layout................................................................55
Figure 26. Example 1.8V/3.3V Power Sequencing Circuit .......................................................56
Figure 27. Power Plane Split Example .....................................................................................57
Figure 28. Combination Host-Side / Device-Side IDE Cable Detection ...................................59
Figure 29. Device-Side IDE Cable Detection............................................................................60
Figure 30. Connection Requirements for Primary IDE Connector ...........................................61
Figure 31. Connection Requirements for Secondary IDE Connector.......................................62
Figure 32. Intel
®
ICH2 AC’97– Codec Connection ...................................................................63
Figure 33. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard...............65
Figure 34. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade...................66
Figure 35. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
One-Codec on CNR ..........................................................................................................66
Figure 36. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
Two-Codecs on CNR ........................................................................................................67
Figure 37. CNR Interface..........................................................................................................69
Figure 38. USB Data Signals....................................................................................................70
Figure 39. SMBus/SMLink Interface.........................................................................................72
Figure 40. PCI Bus Layout Example.........................................................................................73
Figure 41. External Circuitry for the Intel
®
ICH2 RTC...............................................................74
Figure 42. Diode Circuit to Connect RTC External Battery ......................................................76
Figure 43. RTCRST External Circuit for Intel
®
ICH2 RTC........................................................76
Figure 44. RTC Power-well Isolation Control............................................................................78
Figure 45. Intel
®
ICH2 / LAN Connect Section .........................................................................79
Figure 46. Single-Solution Interconnect....................................................................................81
Figure 47. LOM/CNR Interconnect ...........................................................................................81
Figure 48. LAN_CLK Routing Example ....................................................................................82
Figure 49. Trace Routing..........................................................................................................84
Figure 50. Ground Plane Separation ........................................................................................85