Specifications

Intel
®
810E2 Chipset Platform
R
72 Design Guide
Figure 39. SMBus/SMLink Interface
82801BA
Host Controller and
Slave Interface
SMBus
SMBCLK
SPD Data
Temperature on
Thermal Sensor
Network
Interface
Card on PCI
Microcontroller
82850
Motherboard
LAN Controller
Wire OR
(Optional)
SMLink0
SMLink1
SMLink
SMBDATA
smbus-link
Note: Intel does not support external access to the ICH2’s integrated LAN controller via the SMLink interface.
Also, Intel does not support access to the ICH2’s SMBus slave interface by the ICH2’s SMBus host
controller. The following table describes the pull-up requirements for different implementations of the
SMBus and SMLink signals.
Table 21. Pull-up Requirements for SMBus and SMLink
SMBus / SMLink Use Implementation
Alert-on-LAN* signals 4.7-kΩ pull-up resistors to 3.3 VSB are required.
GPIOs Pull-up resistors to 3.3 VSB and the signals must be allowed to change
states on power-up. (For example, on power-up the ICH2 will drive heartbeat
messages until the BIOS programs these signals as GPIOs.) The value of
the pull-up resistors depends on the loading on the GPIO signal.
Not Used 4.7-kΩ pull-up resistors to 3.3 VSB are required.