Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 71
3.16. ISA
Implementations that require ISA support can benefit from the enhancements of the ICH2, while “ISA-
less” designs are not burdened with the complexity and cost of the ISA subsystem. For information
regarding the implementation of an ISA design, contact external suppliers.
3.17. IOAPIC Design Recommendation
UP systems not using the IOAPIC should comply with the following recommendations:
• On the ICH2:
 Tie PICCLK directly to ground.
 Tie PICD0, PICD1 to ground through a 10-kΩ resistor.
• On the processor:
 PICCLK must be connected from the clock generator to the PICCLK pin on the processor.
 Tie PICD0 to 2.5 V through 10-kΩ resistors.
 Tie PICD1 to 2.5 V through 10-kΩ resistors.
3.18. SMBus/SMLink Interface
The SMBus interface on the ICH2 is the same as that on the ICH. It uses two signals, SMBCLK and
SMBDATA, to send and receive data from components residing on the bus. These signals are used
exclusively by the SMBus host controller. The SMBus host controller resides inside the ICH2.
The ICH2 incorporates a new SMLink interface supporting AOL*, AOL2*, and slave functionality. It
uses two signals, SMLINK[1:0]. SMLINK[0] corresponds to an SMBus clock signal and SMLINK[1]
corresponds to an SMBus data signal. These signals are part of the SMB slave interface.
For Alert on LAN (AOL) functionality, the ICH2 transmits heartbeat and event messages over the
interface. When the 82562EM LAN connect component is used, the ICH2’s integrated LAN controller
claims the SMLink heartbeat and event messages and sends them out over the network. An external,
AOL2-enabled LAN controller will connect to the SMLink signals, to receive heartbeat and event
messages as well to as access the ICH2 SMBus slave interface. The slave interface function allows an
external microcontroller to perform various functions. For example, the slave write interface can reset or
wake a system, generate SMI# or interrupts, and send a message. The slave read interface can read the
system power state, read the watchdog timer status, and read system status bits.
Both the SMBus host controller and the SMBus slave interface obey the SMBus protocol, so the two
interfaces can be externally wire-ORed together to allow an external management ASIC to access targets
on the SMBus as well as the ICH2 slave interface. This is performed by connecting SMLink[0] to
SMBCLK and SMLink[1] to SMBDATA, as shown in the following figure. Since the SMBus and
SMLINK are pulled up to VCCSUS3_3, system designers must ensure that they implement proper
isolation for any devices that may be powered down while VCCSUS3_3 is still active (i.e., thermal
sensors).