Specifications

Intel

810E2 Chipset Platform

70 Design Guide

impedance of both wires, resulting in an individual wire presenting a 45-Ω impedance. The trace

impedance can be controlled by carefully selecting the trace width, trace distance from power or

ground planes, and physical proximity of nearby traces.

• USB data lines must be routed as critical signals. The P+/P- signal pair must be routed together,

parallel to each other on the same layer, and not parallel with other non-USB signal traces to

minimize crosstalk. Doubling the space from the P+/P- signal pair to adjacent signal traces will help

to prevent crosstalk. Do not worry about crosstalk between the two P+/P- signal traces. The P+/P-

signal traces must also be the same length. This will minimize the effect of common mode current

on EMI. Lastly, do not route over plane splits.

The following figure illustrates the recommended USB schematic.

Figure 38. USB Data Signals

15k

15 ohm

ICH2

P+

P-

USB Connector

< 1"

90 ohm

45 ohm

Driver

USB Twisted Pair CableTransmission Line

M otherboard Trace

Motherboard Trace

Optional 47 pf

The recommended USB trace characteristics are:

• Impedance ‘Z0’ = 45.4 Ω

• Line Delay = 160.2 ps

• Capacitance = 3.5 pF

• Inductance = 7.3 nH

• Res @ 20° C = 53.9 mΩ

3.15.1. Disabling the Native USB Interface of Intel

ICH2

The ICH2 native USB interface can be disabled. This can be done when an external PCI-based USB

controller is being implemented in the platform. To disable the native USB Interface, ensure the

differential pairs are pulled down thru 15 kΩ resistors, ensure the OC[3:0]# signals are deasserted by

pulling them up weakly to VCC3SBY, and that both function 2 & 4 are disabled via the

D31:F0;FUNC_DIS register. Ensure that the 48 MHz USB clock is connected to the ICH2 and is kept

running. This clock must be maintained even though the internal USB functions are disabled.