Specifications

Intel

810E2 Chipset Platform

64 Design Guide

Clocking is provided from the primary codec on the link via BITCLK, and it is derived from a

24.576-MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator

requirements. BITCLK is a 12.288-MHz clock driven by the primary codec to the digital controller

(ICH2) and any other codec present. That clock is used as the timebase for latching and driving data.

The ICH2 supports wake-on-ring from S1–S5 via the AC’97 link. The codec asserts SDATAIN to wake

the system. To provide wake capability and/or caller ID, standby power must be provided to the modem

codec.

ICH2 has weak pull-downs/pull-ups that are enabled only when the AC-Link Shut-off bit in the ICH2 is

set. This keeps the link from floating when the AC-link is off or when there are no codecs present.

If the Shut-off bit is not set, it means that there is a codec on the link. Therefore, BITCLK and

AC_SDOUT will be driven by the codec and ICH2, respectively. However, AC_SDIN0 and AC_SDIN1

may not be driven. If the link is enabled, it may be assumed that there is at least one codec. If there only

is an on-board codec (i.e., no AMR), then the unused SDIN pin should have a weak (10-kΩ) pull-down

to keep it from floating. If an AMR is used, any SDIN signal could be Not Connected (e.g., with no

codec, both can be NC), then both SDIN pins must have a 10-kΩ pull-down.

Table 18. AC'97 SDIN Pull-down Resistors

System Solution Pull-up Requirements

On-board codec only Pull down the SDIN pin that is not connected to the codec.

AMR only Pull down both SDIN pins.

BOTH AMR and on-board codec Pull down any SDIN pin that could be NC*.

*If the on-board codec can be disabled, both SDIN pins must have pull-downs. If the on-board codec

cannot be disabled, only the SDIN not connected to the on-board codec requires a pull-down.

3.13.1. AC’97 Audio Codec Detect Circuit and Configuration Options

The following provides general circuits to implement a number of different codec configurations. Refer

to Intel’s White Paper Recommendations for ICHx/AC’97 Audio (Motherboard and Communication and

Network Riser) for Intel’s recommended codec configurations.

To support more than two channels of audio output, the ICH2 allows for a configuration where two audio

codecs work concurrently to provide surround capabilities. To maintain data-on-demand capabilities, the

ICH2 AC’97 controller, when configured for 4 or 6 channels, will wait for all the appropriate slot request

bits to be set before sending data in the SDATA_OUT slots. This allows for simple FIFO

synchronization of the attached codecs. It is assumed that both codecs will be programmed to the same

sample rate, and that the codecs have identical (or at least compatible) FIFO depth requirements. It is

recommended that the codecs be provided by the same vendor, upon the certification of their

interoperability in an audio channel configuration.

The following four circuit figures (Figure 33 to Figure 36)show the adaptability of a system with the

modification of R

and R

combined with some basic glue logic to support multiple codec

configurations. This also provides a mechanism to make sure that only two codecs are enabled in a given

configuration and allows the configuration of the link to be determined by BIOS so that the correct PnP

IDs can be loaded.