Specifications

Intel

810E2 Chipset Platform

58 Design Guide

3.11.1. Cabling

• Length of cable: Each IDE cable must be equal to or less than 18”.

• Capacitance: Less than 30 pF

• Placement: A maximum of 6” between drive connectors on the cable. If a single drive is placed on

the cable, it should be placed at the end of the cable. If a second drive is placed on the same cable, it

should be placed on the connector next closest to the end of the cable (6” away from the end of the

cable).

• Grounding: Provide a direct, low-impedance chassis path between the motherboard ground and

hard disk drives.

• ICH2 Placement: The ICH2 must be placed at most 8” from the ATA connector(s).

• PC99 Requirement: Support Cable Select for master-slave configuration is a system design

requirement of Microsoft* PC99. The CSEL signal of each ATA connector must be grounded at the

host side.

3.12. Cable Detection for Ultra ATA/66 and Ultra ATA/100

The ICH2 IDE controller supports PIO, multiword (8237-style) DMA, and Ultra DMA modes

0 through 5. The ICH2 must determine the type of cable present, to configure itself for the fastest

possible transfer mode that the hardware can support.

An 80-conductor IDE cable is required for Ultra ATA/66 and Ultra ATA/100. This cable uses the same

40-pin connector as the old 40-pin IDE cable. The wires in the cable alternate: ground, signal, ground,

signal. All ground wires are tied together on the cable (and they are tied to the ground on the

motherboard through the ground pins in the 40-pin connector). This cable conforms to the Small Form

Factor Specification SFF-8049, which is obtainable from the Small Form Factor Committee.

To determine whether the ATA/66 or ATA/100 mode can be enabled, the ICH2 requires that the system

software attempt to determine the type of cable used in the system. If the system software detects an

80-conductor cable, it may use any Ultra DMA mode up to the highest transfer mode supported by both

the chipset and the IDE device. If a 40-conductor cable is detected, the system software must not enable

modes faster than Ultra DMA Mode 2 (Ultra ATA/33).

Intel recommends that cable detection be performed using a combination host-side/device-side detection

mechanism. Note that host-side detection cannot be implemented on an NLX form factor system, since

this configuration does not define interconnect pins for the PDIAG#/CBLID# from the riser (containing

the ATA connectors) to the motherboard. These systems must rely on the device-side detection

mechanism only.

3.12.1. Combination Host-Side/Device-Side Cable Detection

Host-side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of two

GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal of the IDE

connector to the host is shown in the following figure. All IDE devices have a 10-kΩ pull-up resistor to

5 volts on this signal. Not all GPI and GPIO pins on the ICH2 are 5-volt tolerant. If non 5-volt tolerant

inputs are used, a resistor divider is required to prevent 5 V on the ICH2 or FWH pins. The proper value

of the divider resistor is 10 kΩ (as shown in the following figure).