Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 55
Figure 25. Intel
®
ICH2 Decoupling Capacitor Layout
3.3V Core
1.8V Core
1.8V Standby
3.3V Standby
3.3V Core
1.8V Standby
5V Ref
decouple_cap_layout
3.8. 1.8V/3.3V Power Sequencing
The ICH2 has two pairs of associated 1.8V and 3.3V supplies. These are Vcc1_8, Vcc3_3 and
VccSus1_8, VccSus3_3. These pairs are assumed to power up and power down together. The difference
between the two associated supplies must never be greater than 2.0V. The 1.8V supply may come up
before the 3.3V supply without violating this rule (though this is generally not practical in a desktop
environment, since the 1.8V supply is typically derived from the 3.3V supply by means of a linear
regulator).
One serious consequence of violation of this "2V Rule" is electrical overstress of oxide layers, resulting
in component damage.
The majority of the ICH2 I/O buffers are driven by the 3.3V supplies, but are controlled by logic that is
powered by the 1.8V supplies. Thus, another consequence of faulty power sequencing arises if the 3.3V
supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.8V logic is
powered up. Some signals that are defined as "Input-only" actually have output buffers that are normally
disabled, and the ICH2 may unexpectedly drive these signals if the 3.3V supply is active while the 1.8V
supply is not.