Specifications

Intel
®
810E2 Chipset Platform
R
50 Design Guide
Figure 20. Display Cache (Topology 3)
1Mx16
1Mx16
DE
F
F
22 Ohms
Table 15. Display Cache Routing (Topology 3)
Trace (units=mils) D (inches) E (inches) F (inches)
Signal Topology Width Spacing Length Min Max Min Max
TCLK 3 5 7 0.5 1.5 2.5 0.75 1.25
Figure 21. Display Cache (Topology 4)
GH
33 Ohms
OCLK
RCLK
Table 16. Display Cache Routing (Topology 4)
Trace (units=mils) G (inches) H (inches)
Signal Topology Width Spacing Length Min Max
OCLK 4 5 6 0.5 3.25 3.75