Specifications
Intel
®
810E2 Chipset Platform
R
Design Guide 5
3.21.2.2.
Power and Ground Connections .................................................... 85
3.21.2.3. A 4-Layer Board Design ................................................................. 86
3.21.2.4. Common Physical Layout Issues ................................................... 87
3.21.3. Intel
®
82562EH Home/PNA* Guidelines ..................................................... 88
3.21.3.1. Power and Ground Connections .................................................... 88
3.21.3.2. Guidelines for Intel
®
82562EH Component Placement .................. 89
3.21.3.3. Crystals and Oscillators .................................................................. 89
3.21.3.4. Phoneline HPNA Termination......................................................... 89
3.21.3.5. Critical Dimensions......................................................................... 91
3.21.4. Intel
®
82562ET / 82562EM Guidelines ........................................................ 92
3.21.4.1. Guidelines for Intel
®
82562ET / 82562EM Component Placement 92
3.21.4.2. Crystals and Oscillators .................................................................. 93
3.21.4.3. Intel
®
82562ET / 82562EM Termination Resistors ......................... 93
3.21.4.4. Critical Dimensions......................................................................... 94
3.21.4.5. Reducing Circuit Inductance........................................................... 95
3.21.4.6. Intel
®
82562ET/EM Disable Guidelines .......................................... 96
3.21.5. Intel
®
82562ET / 82562EH Dual Footprint Guidelines................................. 97
3.22. LPC/FWH ...................................................................................................................... 99
3.22.1. In-Circuit FWH Programming...................................................................... 99
3.22.2. FWH Vpp Design Guidelines ...................................................................... 99
3.23. FWH Decoupling ......................................................................................................... 100
3.24. Processor PLL Filter Recommendation ...................................................................... 100
3.24.1. Processor PLL Filter Recommendation .................................................... 100
3.24.2. Topology.................................................................................................... 100
3.24.3. Filter Specification ..................................................................................... 100
3.24.4. Recommendation for Intel
®
Platforms ....................................................... 102
3.24.5. Custom Solutions ...................................................................................... 104
3.25. RAMDAC/Display Interface ......................................................................................... 105
3.25.1. Reference Resistor (Rset) Calculation...................................................... 106
3.25.2. RAMDAC Board Design Guidelines .......................................................... 106
3.26. DPLL Filter Design Guidelines .................................................................................... 108
3.26.1. Filter Specification ..................................................................................... 109
3.26.2. Recommended Routing/Component Placement....................................... 110
3.26.3. Example LC Filter Components ................................................................ 110
4. Advanced System Bus Design................................................................................................. 113
4.1. AGTL+ Design Guidelines........................................................................................... 113
4.1.1. Initial Timing Analysis................................................................................ 114
4.1.2. Determine General Topology, Layout, and Routing Desired..................... 117
4.1.3. Pre-Layout Simulation ............................................................................... 117
4.1.3.1. Methodology ................................................................................. 117
4.1.3.2. Sensitivity Analysis ....................................................................... 117
4.1.3.3. Monte Carlo Analysis.................................................................... 118
4.1.3.4. Simulation Criteria ........................................................................ 118
4.1.4. Place and Route Board ............................................................................. 119
4.1.4.1. Estimate Component to Component Spacing for AGTL+ Signals 119
4.1.4.2. Layout and Route Board............................................................... 119
4.1.5. Post-Layout Simulation ............................................................................. 120
4.1.5.1. Intersymbol Interference............................................................... 121
4.1.5.2. Crosstalk Analysis ........................................................................ 121
4.1.5.3. Monte Carlo Analysis.................................................................... 121
4.1.6. Validation................................................................................................... 121
4.1.6.1. Measurements.............................................................................. 121
4.1.6.2. Flight Time Simulation .................................................................. 122