Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 49
3.5. Display Cache Interface
Figure 18. Display Cache (Topology 1)
A
1Mx16
3.5.1. Display Cache Solution Space
Table 13. Display Cache Routing (Topology 1)
Trace (mils) A (inches)
Signal Topology Width Spacing Min Max
LMD[31:0], LDQM[3:0] 1 5 7 1 5
NOTES:
1. Trace Length (inches)
Figure 19. Display Cache (Topology 2)
1Mx16
1Mx16
B
C
C
Table 14. Display Cache Routing (Topology 2)
Trace (units=mils) B (inches) C (inches)
Signal Topology Width Spacing Min Max Min Max
LMA[11:0], LWE#, LCS#, LRAS#, LCAS# 2 5 7 1 3.75 0.75 1.25