Specifications
Intel
®
810E2 Chipset Platform
R
46 Design Guide
3.4. System Memory Layout Guidelines
3.4.1. System Memory Solution Space
Figure 15. System Memory Topologies
F
G
G
DIMM0 DIMM1
Topology 1
Topology 2
Topology 3
Topology 4
Topology 5
GMCH
A
B
10 ohm
A
C
10 ohm
A
D
A
D
A
E
Table 12. System Memory Routing
Trace Lengths (inches)
Trace (mils) A B C D E F G
Signal Top. Width Space Max Min Max Min Max Min Max Min Max Min Max Min Max
SCS[3:2]# Opt.1 5 10 8
3 5
1.5 2
Opt.2 5 10 8
2.2 5
1.5 1.8
Opt.3 5 10 8
1.6 5
1.15 1.5
SCS[1:0]# Opt.1 4 10 8
3 5
1.5 2
Opt.2 4 10 8
2.2 5
1.5 1.8
Opt.3 4 10 8
1.6 5
1.15 1.5
SMAA[7:4]
1 10 8 0.5 0.5 2
SMAB[7:4]#
2 10 8 0.5
0.5 2
SCKE[1:0]
3 10 8
1 2.5
0.4 1
SMD[63:0],
SDQM[7:0]
3 5 7
1 3
0.4 1
SCAS#, SRAS#,
SWE#
3 5 7
1 3.5
0.4 1
SBS[1:0],
SMAA[11:8, 3:0]
3 5 7
1 2.5
0.4 1
NOTES:
1. It is recommended to add 10 Ω series resistors to the MAA[7:4] and the MAB[7:4] lines, as close as possible to
GMCH for signal integrity.