Specifications

Intel
®
810E2 Chipset Platform
R
Design Guide 41
3. Layout and Routing Guidelines
This chapter describes motherboard layout and routing guidelines for 810E2 chipset systems, except for
the processor layout guidelines. For the PGA370 processor specific layout guidelines, refer to Chapter 2.
This chapter does not discuss the functional aspects of any bus or the layout guidelines for an add-in
device.
Note: If the guidelines listed in this document are not followed, it is very important that thorough signal
integrity and timing simulations are completed for each design. Even when the guidelines are followed,
critical signals are recommended to be simulated to ensure proper signal integrity and flight time. Any
deviation from these guidelines should be simulated.
3.1. General Recommendations
The trace impedance typically noted (i.e., 60 Ω ±15%) is the “nominal” trace impedance for a 5 mil wide
trace (i.e., the impedance of the trace when not subjected to the fields created by changing current in
neighboring traces). When calculating flight times, it is important to consider the minimum and
maximum impedance of a trace based on the switching of neighboring traces. Using wider spaces
between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce
settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces, the
signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects of trace-
to-trace coupling, the routing guidelines documented in this chapter should be followed.
Additionally, these routing guidelines are created using a PCB stack-up similar to that illustrated in the
following figure. If this stack-up is not used, extremely thorough simulations of every interface must be
completed. Using a thicker dielectric (prepreg) will make routing very difficult or impossible.
3.2. Nominal Board Stackup
The 810E2 chipset platform requires a board stackup yielding a target impedance of 60 Ω ±15% with a 5
mil nominal trace width. The following figure presents an example stackup to achieve this. It is a 4-layer
fabrication construction using 53% resin, FR4 material.